This document was scanned from a copy lent by Computer History Museum.
OCTAL. CODE  MNE MONIC  AD DRESS  NAME  PAGE 
00  PS  .  Program stop  323 
010  RJ  K  Return jump to K  343 
011  REC  Bj + K  Read Extended Core Storage  346 
012  WEC  Bj + K  Write Extended Core Storage  347 
02*  JP  Bi + K  Jump to Bi + K  344 
030**  ZR  Xj K  Jump to K if Xj = 0  344 
031**  NZ  Xj K  Jump to K if Xj <>0  344 
032**  PL  Xj K  Jump to K if Xj = plus (positive)  344 
033**  NG  Xj K  Jump to K if Xj = negative  344 
034**  IR  Xj K  Jump to K if Xj is in range  344 
035**  OR  Xj K  Jump to K if Xj is out of range  344 
036**  DF  Xj K  Jump to K if Xj is definite  344 
037**  ID  Xj K  Jump to K if Xj is indefinite  344 
04*  EQ  Bi Bj K  Jump to K if Bi = Bj  345 
05*  NE  Bi Bj K  Jump to K if Bi <> Bj  345 
06*  GE  Bi Bj K  Jump to K if Bi => BI  345 
07*  LT  Bi Bj K  Jump to K if Bi < Bj  345 
10  BXi  Xj  Transmit Xj to Xi  329 
11  BXi  Xj * Xk  Logical Product of Xj & Xk to Xi  329 
12  BXi  Xj + Xk  Logical sum of Xj & Xk to Xi  330 
13  BXi  Xj  Xk  Logical difference of Xj & Xk to Xi  330 
14  BXi  Xk  Transmit the comp. of Xk to Xi  330 
15  BXi  Xk * Xj  Logical product of Xj & Xk comp. to Xi  331 
16  BXi  Xk + Xj  Logical sum of Xi & Xk comp. of Xi  331 
17  BXi  Xk  Xj  Logical difference of Xj & Xk comp. to Xi  332 
20  LXi  jk  Left shift Xi, jk places  332 
21  AXi  jk  Arithmetic right shift Xi, jk places  332 
22  LXi  Bj Xk  Left shift Xk nominally Bj places to Xi  333 
23  AXi  Bj Xk  Arithmetic right shift Xk nominally Bj places to Xi  333 
24  NXi  Bj Xk  Normalize Xk in Xi and Bj  334 
25  ZXi  Bj Xk  Round and normalize Xk in Xi and Bj  334 
26  UXi  B Xk  Unpack Xk to Xi and Bj  335 
27  PXi  Bj Xk  Pack Xi from Xk and Bj  336 
30  FXi  Xj + Xk  Floating sum of Xj and Xk to Xi  337 
31  FXi  Xj  Xk  Floating difference Xj and Xk to Xi  337 
32  DXi  Xj + Xk  Floating DP sum of Xj and Xk to Xi  338 
33  DXi  Xj  Xk  Floating DP difference of Xj and Xk to Xi  338 
34  RXi  Xj + Xk  Round floating sum of Xj and Xk to Xi  338 
35  RXi  Xj  Xk  Round floating difference of Xj and Xk to Xi  339 
36  IXi  Xj + Xk  Integer sum of Xj and Xk to Xi  328 
37  IXi  Xj  Xk  Integer difference of Xj and Xk to Xi  328 
40  FXi  Xj * Xk  Floating product of Xj and Xk to Xi  340 
41  RXi  Xj * Xk  Round floating product of Xj and Xk to Xi  340 
42  DXi  Xj * Xk  Floating DP product of Xj and Xk to Xi  341 
43  MXi  jk  Form mask in Xi, jk bits  336 
44  FXi  Xj / Xk  Floating divide Xj by Xk to Xi  341 
45  RXi  Xj / Xk  Round floating divide Xj by Xk to Xi  342 
46  NO  .  No operation (Pass)  323 
47  CXi  Xk  Count the number of 1's in Xk to Xi  328 
50  SAi  Aj + K  Set Ai to Aj + K  324 
51  SAi  Bj + K  Set At to Bj + K  324 
52  SAi  Xj + K  Set At to Xj + K  324 
53  SAi  Xj + Bk  Set Ai to Xj + Bk  324 
54  SAi  Aj + Bk  Set At to Aj + Bk  324 
55  SAi  Aj  Bk  Set Ai to Aj  Bk  324 
56  SAi  Bj + Bk  Set At to Bj + Elk  324 
57  SAi  Bj  Bk  Set At to Bj  Bk  324 
60  SBi  Aj + K  Set Bi to Aj + K  326 
61  SBi  Bj + K  Set Bi to Bj + K  326 
62  SBi  Xj + K  Set Bi to Xj + K  326 
63  SBi  Xj + Bk  Set Bi to Xj + Bk  326 
64  SBi  Aj + Bk  Set Bi to Aj + Bk  326 
65  SBi  Aj  Bk  Set Bi to Aj  Bk  326 
66  SBi  Bj + Bk  Set Bi to Bj + Bk  326 
67  SBi  Bj = Bk  Set Bi to Bj  Bk  326 
70  SXi  Aj + K  Set Xi to Aj + K  326 
v71  SXi  Bj + K  Set Xi to Bj + K  326 
72  SXi  Xj + K  Set Xi to Xj + K  326 
73  SXi  Xj + Bk  Set Xi to Xj + Bk  327 
74  SXi  Aj + Bk  Set Xi to Aj + Bk  327 
75  SXi  Aj  Bk  Set Xi to Aj  Bk  327 
76  SXi  Bj + Bk  Set Xi to Bj + Bk  327 
77  SXi  Bj  Bk  Set Xi to Bj  Bk  32 7 
MNE MONIC  OCTAL. CODE  AD DRESS  NAME  PAGE 
AXi  21  jk  Arithmetic right shift Xi, jk places  332 
AXi  23  Bj Xk  Arithmetic right shift Xk nominally Bj places to Xi  333 
BXi  10  Xj  Transmit Xj to Xi  329 
BXi  11  Xj * Xk  Logical product of Xj and Xk to Xi  329 
BXi  12  Xj + Xk  Logical sum of Xj and Xk to Xi  330 
BXi  13  Xj  Xk  Logical difference of Xj and Xk to Xi  330 
BXi  14  Xk  Transmit the comp. of Xk to Xi  330 
BXi  15  Xk Xj  Logical product of Xj and Xk comp. to Xi  331 
BXi  16  Xk + Xj  Logical sum of Xj and Xk comp. to Xi  331 
BXi  17  Xk  Xj  Logical difference of Xj and Xk comp, to Xi  332 
CXi  47  Xk  Count the number of 1's in Xk to Xi  328 
DF**  036  Xj K  Jump to K if Xj is definite  344 
DXi  32  Xj + Xk  Floating DP sum of Xj and Xk to Xi  338 
DXi  33  Xj  Xk  Floating DP difference of Xj and Xk to Xi  338 
DXi  42  Xj ' Xk  Floating DP product of Xj and Xk to Xi  341 
EQ*  04  Bi Bj K  Jump to K if Bi = Bj  345 
FXi  30  Xj + Xk  Floating sum of Xj and Xk to Xi  337 
FXi  31  Xj  Xk  Floating difference of Xj and Xk to Xi  337 
FXi  40  Xj * Xk  Floating product of Xj and Xk to Xi  340 
FXi  44  Xj / Xk  Floating divide Xj by Xk to Xi  341 
GE*  06  Bi Bj K  Jump to K if Bi Bj  345 
ID**  037  Xj K  Jump to K if Xj is indefinite  344 
IR**  034  Xj K  Jump to K if Xj is in range  344 
IXi  36  Xj + K  Integer sum of Xj and Xk to Xi  328 
IXi  37  Xj  Xk  Integer difference of Xj and Xk to Xi  328 
JP*  02  Bi + K  Jump to Bi + K  344 
LT*  07  Bi Bj K  Jump to K if Bi < Bj  345 
LXi  20  jk  Left shift Xi, jk places  332 
LXi  22  Bj Xk  Left shift Xk nominally Bj places to Xi  333 
MXi  43  jk  Form mask in Xi, jk bits  336 
NE*  05  Bi Bj K  Jump to K if Bi <> Bj  345 
NG**  033  Xj K  Jump to K if Xj = negative  344 
NO  46  .  No operation (Pass)  323 
NXi  24  Bj Xk  Normalize Xk in Xi and Bj  334 
NZ**  031  Xj K  Jump to K if Xj <> 0  344 
OR**  035  Xj K  Jump to K if Xj is out of range  344 
PL**  032  Xj K  Jump to K if Xj  plus (positive)  344 
PS  00  .  Program stop  323 
PXi  27  Bj Xk  Pack Xi from Xk and Bj  336 
REC  011  Bj + K  Read extended core  346 
RJ  010  K  Return jump to K  343 
RXi  34  Xj + Xk  Round floating sum of Xj and Xk to Xi  338 
RXi  35  Xj  Xk  Round floating difference to Xj and Xk to Xi  339 
RXi  41  Xj * Xk  Round floating product to Xj and Xk to Xi  340 
RXi  45  Xj / Xk  Round floating divide Xj by Xk to Xi  342 
SAi  50  Aj + K  Set Ai to Aj + K  324 
SAi  51  Bj + K  Set At to Bj + K  324 
SAi  52  Xj + K  Set At to Xj + K  324 
SAi  53  Xj + Bk  Set Ai to Xj + Bk  324 
SAi  54  Aj + Bk  Set At to Aj + Bk  324 
SAi  55  Aj  Bk  Set Ai to Aj  Bk  324 
SAi  56  Bj + Bk  Set Ai to Bj + Bk  324 
SAi  57  Bi  Bk  Set Ai to Bj  Bk  324 
SBi  60  Aj + K  Set Bi to Aj + K  326 
SBi  61  Bj + K  Set Bi to Bj + K  326 
SBi  62  Xj + K  Set Bi to Xj + K  326 
SBi  63  Xj + Bk  Set Bi to Xj + Bk  326 
SBi  64  Aj + Bk  Set Bi to Aj + Bk  326 
SBi  65  Aj  Bk  Set Di to Aj  Bk  326 
SBi  66  Bj + Bk  Set Bi to Bj + Bk  326 
SBi  67  Bj  Bk  Set Bi to Bj  Ilk  326 
SXi  70  Aj + K  Set Xi to Aj + K  326 
SXi  71  Bj + K  Set XI to Bj + K  326 
SXi  72  Xj + K  Set Xi to Xi + K  326 
SXi  73  Xj + Bk  Set Xi to Xj + Bk  327 
SXi  74  Aj + Bk  Set Xi to Aj + Bk  327 
SXi  75  Aj  Bk  Set Xi to Aj  Bk  327 
SXi  76  Bj + Bk  Set Xi to Bj + Bk  327 
SXi  77  Bj  Bk  Set Xi to Bj  Bk  327 
UXi  16  Bj Xk  Unpack Xk to Xi and Bj  335 
WEC  012  Bj + K  Write extended core  347 
ZR**  030  Xj K  Jump to K if Xj = 0  344 
ZXi  25  Bj Xk  Round and normalize Xk in Xi and Bj  334 

Introduction  11 
Systems Characteristics Summary  13 
14 
14 
15 
16 
17  
Systems Options  18 
.  
Organization  21 
Address Format  21 
Central Memory Access  21 
Memory Protection  22 
.  
Organization  31 
Central Processor Programming  34 
35 
35 
36 
39 
311 
315 
321 
322 
323 
324 
328 
329 
332 
337 
343 
346 
. 
Organization  41 
Peripheral Processor Programming  46 
46 
46 
48 
49 
410 
411 
413 
416 
416 
419 
422 
424 
427 
432 
435 
439 
. 
Introduction  51 
Hardware Provisions for Interrupt  51 
51 
51 
52 
. 
Introduction  61 
Dead Start  61 
61 
62 
62  
Console  6 4 
64 
64 
Appendix A  Augmented I/O Buffer and Control (6416) 
Appendix B  Instruction Execution Times 
Appendix C  NonStandard Floating Point Arithmetic 
Appendix D  Compass Mnemonics 
11  CONTROL DATA 6400/6500 6600 Computer Systems  11 
12  Concurrent Operations in the 6400/6500/6600  12 
13  Block Diagram of 6600 System  16 
14  Block Diagram of 6400 and 6500 Systems  17 
21  Memory Map  23 
31  Central Processor Instruction Formats  36 
32  Central Processor Operating Registers  37 
33  Exchange Jump Package  39 
34  Detecting and Handling Central Processor Stops  314 
41  Flow Chart: 6400/6500/6600 Systems  41 
42  Peripheral and Control Processors  45 
61  Dead Start Panel  63 
62  Display Console  65 
63  Sample Display  66 
31  Central Processor Differences  31 
32  Functional Units  35 
33  Exit Mode: Address Out of Bounds  313 
34  Range of Permissible Exponents  316 
35  Indefinite Forms  317 
36  Overflow and Underflow Conditions  320 
37  Central Processor Instruction Designators  322 
41  Addressing Modes for Peripheral and Control Processor Instructions  48 
42  Peripheral and Control Processor Instruction Designators  410 
Display console (foreground)  includes a keyboard for manual input and operator control and two 10inch display tubes for display of problem status and operator directives.
Mainframe (center)  contains 10 Peripheral and Control Processors, Central Processor, Central Memory, some 1/O synchronizers. The main frame in this photo is that of the 6600 Computer System; the mainframesfor the 6400 and 6500 systems differ in physical appearance, depending on options included in the systems.
CONTROL DATA 607 Magnetic Tape Transport (left front)  1 / 2inch magnetic tape units for supplementary storage; binary or BCD data handled at 200, 556, or 800 bpi.
CONTROL DATA 626 Magnetic Tape Transport (left rear)  1inch magnetic tape units for supplementary storage; binary data handled at 800 bpi.
CONTROL DATA 405 Card Reader (right front)  reads binary or BCD cards at 1200 card per minute rate.
Disk file (right rear)  supplementary mass storage device; holds 500 million bits of information.
The CONTROL DATA* 6400, 6500, and 6600 Computer Systems are three largescale, solidstate, generalpurpose digital computing systems. The advanced design techniques incorporated in these systems provide for extremely fast solutions to data processing, scientific, and control center problems, as well as multiprocessing, timesharing, and management information applications.
Each of the computing systems has at least eleven independent computers
(Figure 11). Ten of these, constructed with the peripheral and operating system
in mind, are Peripheral and Control Processors. Each of these ten has separate
memory and can execute programs independently of each other or the Central
Processor.
Figure 11. CONTROL DATA 6400/6500/6600 Computer Systems
In solving a problem, one or more Peripheral and Control Processors are used
for high speed information transfer in and out of the system and to provide
operator control. A number of problems may operate concurrently by timesharing
the Central Processor. (To facilitate this, the Central Processor may operate in
Central Memory only within address bounds prescribed by a Peripheral and Control
Processor.) Further concurrency is obtained within the Central Processor by
parallel action of various functional segments. Similarly, Central Memory is
organized in 32 logically independent banks of 4096 words (60bit). Several
banks may be in operation simultaneously, thereby minimizing execution time. The
multiple operating modes of all segments of the computer, in combination with
highspeed transistor circuits, produce a very high overall computing speed.
Figure 12.Concurrent Operations in the 6400/6500/6600
Add  Shift 
Multiply  Branch 
Multiply  Boolean 
Divide  Increment 
Long add  Increment 
6400 and 6500
Common Central Processor Characteristics
The foregoing summary of characteristics assumed a 6400, 6500, or 6600 system with 10 Peripheral and Control Processors, a Central Processor (except for the 6500 system with its two identical Central Processors), and Central Memory with 131, 072 words (60bit) of magnetic core storage.
Options listed below are available within each system unless otherwise noted.
Central Memory is organized into 32K, 65K, or 131K words (60bit) in 8, 16, or 32 banks of 4096 words each. The banks are logically independent, and consecutive addresses go to different banks. Banks may be phased into operation at minor cycle intervals, resulting in very high Central Memory operating speed. The Central Memory address and data control mechanisms permit a word to move to or from Central Memory every minor cycle.
The location of each word in Central Memory is identified by an assigned number (address), which consists of 18 bits. Address formats are shown below for 8bank(32K), 16bank (65K), and 32bank (131K) systems. Within the address format, the bank portion specifies one of 8, 16, or 32 banks; the 12bit address defines one of 4096 separate locations within the specified bank. Addresses written or compiled in the conventional manner reference consecutive banks and hence make most efficient use of the bank phasing feature.
References to Central Memory from all areas of the system (Central Processor and Peripheral and Control Processors) go to a common address clearing house called a stunt box and are sent from there to all banks in Central Memory. The stunt box accepts addresses from the various sources under a priority system and at a maximum rate of one address every minor cycle. *Minor cycle=100 ns
All Central Processor references to Central Memory for new instructions, or to read and store data, are made relative to the Reference Address. The Reference Address defines the lower limit of a Central Memory program. Changes to the Reference Address permit easy relocation of programs in Central Memory.
The relationship between absolute memory address, relative memory address,
Reference Address (RA), and Field Length (FL) is indicated in Figure 21.
Figure
21. Memory Map
The following relationships must be true if the program is to operate within its bounds:
An optional exit condition (EM in the Exchange Jump package) allows the Central Processor to stop on a memory reference outside the limits expressed above.
The Central Processor is an extremely highspeed arithmetic processor which communicates only with Central Memory. It consists (functionally) of an arithmetic unit and a control unit. The arithmetic unit contains all logic necessary to execute the arithmetic, manipulative and logical operations. The control unit directs the arithmetic operations and provides the interface between the arithmetic unit and Central Memory. It also performs instruction fetching, address preparation, memory protection, and data fetching and storing.
The Central Processor is isolated from the Peripheral and Control Processors and is thus free to carry on highspeed computation unencumbered by input/output requirements.
The organization of the Central Processor in the 6400 system differs from the 6600 Central Processor in two important respects. The 6500 system has two Central Processors; each similar to the 6400 Central Processor. Central Processor differences are tabulated in Table 31.
SYSTEM  INSTRUCTION REGISTERS  ARITHMETIC SECTION 
6400 and 6500 Central Processors  Instruction Buffer Register; holds one 60bit instruction word.  Unified Arithmetic Section; executes instructions in serial order. Requires no reservation control. 
6600 Central Processor  Instruction Stack; holds eight 60bit instruction words.  Ten functional (arithmetic & logical) units; operate concurrently on unrelated instructions. Require reservation control. 
The following discussion details the operation of the Central Processor in the 6600 system. With the exception of differences noted in the above table (and the inherent effects on Central Processor operation), the 6400 system Central Processor operation is identical, Each of the two 6500 Central Processors operates identically with the 6400 Central Processor.
Eight 60bit registers are provided to hold instructions (6600), thereby limiting the number of memory reads for repetitive instructions, especially in inner loops. Multiple banks of Central Memory are also provided to minimize memory reference time. References to different banks of memory may be handled without wait.
Speed of operation in a conventional computer is also limited by the serial manner in which instructions are executed; instructions are executed sequentially in time with little or no concurrency.
In the 6600 Computer System, this delay is minimized by providing 10 arithmetic (functional) units and a reservation control. Unrelated instructions are executed simultaneously, provided no conflicts exist in the arithmetic units.
The 6400 or 6500, with its unified arithmetic section, executes instructions serially, with little concurrency.
Nearly all Central Memory references for information or instructions are made on an implicit or secondary basis. Instructions are fetched from memory only if the instruction registers are nearly empty (or when ordered by a branch). Information is brought to or from the operand registers only when appropriate address registers are referenced during the course of a program. Such references are also accounted for in the reservation control.
Central Processor program instructions are stored in Central Memory. A 60bit memory location may hold 60 data bits, four 15bit instructions, two 30bit instructions or a combination of 15 or 30bit instructions. Figure 31 shows all instruction combinations in a 60bit word and the two instruction word formats.
The Central Processor reads 60bit words from Central Memory and stores them in an instruction stack which is capable of holding up to eight 60bit words.
Each instruction in turn is sent to a series of instruction registers for interpretation and testing and is then issued to one of 10 functional units for execution. The functional units obtain the instruction operands from and store results in the 24 operating registers. The reservation control records active operating registers and functional units to avoid conflicts and insure that the original instructions do not get out of order.
The 10 functional units in the 6600 system handles the requirements of the various instructions. The Multiply and Increment units are duplexed, and an instruction is sent to the second unit if the first is busy. The general function of each unit is listed in Table 32.
UNIT  GENERAL FUNCTION 
Branch  Handles all jumps or branches from the program. 
Boolean  Handles the basic logical operations of transfer, logical product, logical sum, and logical difference. 
Shift  Handles operations basic to shifting. This includes left (circular) and right (endoff sign extension) shifting, and Normalize, Pack, and Unpack floating point operations. The unit also provides a mask generator. 
Add  Performs floating point addition and subtraction on floating point numbers or their rounded representation. 
Long add  Performs one's complement addition and subtraction of 60bit fixed point numbers. 
Multiply  Performs floating point multiplication on floating point numbers or their rounded representation. 
Divide  Performs floating point division of floating point quantities or their rounded representation. Also sums the number of "1's" in a 60bit word. 
Increment  Performs one's complement addition and subtraction of 18bit numbers. 
Groups of bits in an instruction are identified by the letters f, m, i, j, k, and K (Figure 31). All letters represent octal digits except K,which is an 18bit constant. The f and m digits are the operation code and identify the type of instruction. In a few instructions the i designator becomes a part of the operation code.
In the 6600, it is permissible to pack the upperorder 15 bits (fmij portion) of a 30bit instruction in the lowerorder 15bit portion of an instruction word. When this 30 bit instruction is executed, the lowerorder 15bits of K are taken from the upperorder 15 bits of the instruction word. In the 6400 and 6500, any 30bit instruction with its fmij portion packed in the lowerorder 15 bits of an instruction word will be executed as a STOP instruction.
Operating Registers In order to provide a compact symbolic language, the 24 operating registers are identified by letters and numbers:
The operand registers hold operands and results for servicing the functional units. Five registers (X1  X5) hold read operands from Central Memory, and two registers (X6  X7) hold results to be sent to Central Memory (Figure 32). Operands and results transfer between memory and these registers as a result of placing a quantity into a corresponding address register (Al  A7).
Placing a quantity into an address register A1  A5 produces an immediate
memory reference to that address and reads the operand into the corresponding
operand register X1  X5. Similarly, placing a quantity into address register A6
or A7 stores the word in the corresponding X6 or X7 operand register in the new
address.
Figure 32. Central Processor Operating Registers
The increment instructions place a result in address register Ai (where "i" = 0 to 7) in three ways:
The A0 and X0 registers are independent and have no connection with Central Memory. They may be used for scratch pad or intermediate results. Note the special use of A0 and X0 when executing Extended Core Storage communication instructions.
The B registers have no connection with Central Memory. The BO register is fixed to provide a constant zero (18bit) which is useful for various tests against zero, providing an unconditional jump modifier, etc. In general, the n registers provide means for program indexing. For example, B4 may store the number of times a program loop has been traversed, thereby providing a terminal condition for a program exit.
An Exchange Jump instruction from a Peripheral and Control Processor enters initial values in the operating registers to start Central Processor operation. Subsequent address modification instructions executed in the increment functional units provide the addresses required to fetch and store data.
Program Address
An 18bit P register serves as a program
address counter and holds the address for each program step. P is advanced to
the next program step in the following ways:
All branch instructions to a new program start the program with the instruction located in the highest order position of the 60bit word.
The Central Processor enters the information about a new program into the appropriate registers and stores the corresponding and current information from the interrupted program at the same 16 locations in Central Memory. Hence, the controlling information for two programs is exchanged. A later Exchange Jump may return an interrupted program to the Central Processor for completion. The normal relation of the A and X registers (described earlier) is not active during the Exchange Jump so that the new entries in A are not reflected into changes in X.
EXAMPLE:PROGRAMMING NOTE When an Exchange Jump interrupts the Central Processor, several steps occur to insure leaving the interrupted program in a usable state for reentry:
A subsequent Exchange Jump can then reenter the interrupted program at the point it was interrupted, with no loss of program continuity.
 Issue of instructions halts after issuing all instructions from the current instruction word in the instruction stack.
 The Program Address register, P, is set to the address of the next instruction word to be executed.
 The issued instructions are executed, and then
 The parameters for the two programs are exchanged.
To preserve the integrity of an "instack" loop (in the event of an Exchange Jump), it is illegal to modify the contents of any memory address which holds an executable instruction (or instruction word) contained within the loop.
All Central Processor references to Central Memory for new instructions, or to fetch and store data, are made relative to the Reference Address. This allows easy relocation of a program in Central Memory. The Reference Address or beginning address and the Field Length define the Central Memory limits of the program. An Exit Selection allows the Central Processor to stop on a memory reference outside these limits.
EM = 000000  Disable Exit mode  no Exit selections made. 
EM = 010000  Address out of range 

EM = 020000  Operand out of range  floating point arithmetic unit received an infinite operand (see Range Definitions under Floating Point Arithmetic following). 
EM = 030000  Address or operand out of range 
EM = 040000  Indefinite operand  floating point arithmetic unit (Add, Multiply, or Divide) attempted to use an indefinite operand (see Range Definitions, page 317). 
EM = 050000  Indefinite operand or address out of range 
EM = 060000  Indefinite operand or operand out of range 
EM = 070000  Indefinite operand or operand or address out of range 
Typically, the Reference Address (RA) for any program is left cleared to all zeros. When an error exit is taken, the Central Processor records at RA the exit condition (upper 2 octal digits only) and the Program Address at exit time (refer to the format below).
The contents of RA are then read up, interpreted as a Stop instruction, and the Central Processor stops.NOTE
The Exit condition(s) recorded at RA comprises all the Exit conditions detected since the last Exchange Jump, regardless of whether they were selected. Thus, com binations of error Exit conditions (03, 05, 06 or 07) can appear at RA:
 When at least one Exit condition was selected and the selected condition plus another condition occur red since the last Exchange Jump, or
 When more than one Exit condition was selected and each occurred in the same minor cycle.
On an Address Out of Range, hardware action differs from that outlined above. In some cases, a stop occurs when an address is out of bounds even though an Exit mode stop is not selected for this condition. Table 33 summarizes hardware action for operations which may reference addresses that are out of bounds.
. 
 
OPERATION  EXIT MODE SELECTED  EXIT MODE NOT SELECTED 
RNI to an address that is outof bounds (occurs when an instr. is located in absolute address (RA + FL)  1). 


Branch to an address that is outofbounds. 


Read Operand 


Write Operand 


Action After Exit Mode or Normal Stop
Typically, a
Peripheral and Control Processor periodically searches for an unchanging Central
Processor Program Address register (any value) to determine if the Central
Processor has stopped. Once it has been determined that the Central Processor
has stopped, the examining Peripheral and Control Processor can transfer control
to an error routine to determine the nature of the condition causing the Stop.
Figure 34 illustrates sample steps for processing Central Processor stops
(either Exit mode or normal).
Figure
34. Detecting and Handling Central Processor Stops
Format
Floating point arithmetic takes advantage of the
ability to express a number with the general expression kB^{n} where:
The base number is constant (2) for binarycoded quantities and is not
included in the general format. The 60bit floatingpoint format is shown below.
The binary point is considered to be to the right of the coefficient, thereby
providing a 48bit integer coefficient, the equivalent of about 14 decimal
digits. The sign of the coefficient is carried in the highest order bit of the
packed word. Negative numbers are represented in one's complement notation.
The 11bit exponent
carries a bias of 2^{10} (2000_{8}) when packed in the floating
point word (biased exponent sometimes referred to as characteristic). The bias
is removed when the word is unpacked for computation and restored when a word is
packed into floating format. Table 34 lists (in decimal and octal notation) the
complete range of permissible exponents and the octal form of the corresponding
positive and negative floating point words.
Thus, a number with a true exponent of 342 would appear as 2342; a number with a true exponent of 160 would appear as 1617. Exponent arithmetic is done in one's complement notation. Floating point numbers can be compared for equality and threshold.
Normalizing and Rounding
Normalizing a floating point
quantity shifts the coefficient left until the most significant bit is in bit
47. Sign bits are entered in the loworder bits of the coefficient as it is
normalized. Each shift decreases the exponent by one.
A round bit is added (optionally) to the coefficient during an arithmetic process and has the effect of increasing the absolute value of the operand or result by onehalf the value of the least significant bit. Normalizing and rounding are not automatic during pack or unpack operations so that operands and results may not be normalized.
Single and Double Precision
The floating point arithmetic
instructions generate doubleprecision results. Use of unrounded operations
allows separate recovery of upper and lower half results with proper exponents;
only upper half results can be obtained with rounded operations.
Double length registers appear as follows:
A result the exponent of which is less than the lower limit of octal 0000 (underflow case) is treated as a zero quantity. This quantity is packed with a zero exponent and zero coefficient. No exit is provided for underflow. A result with an exponent of octal 0000 and a coefficient which is not zero is a nonzero quantity and is packed with a zero exponent and the nonzero coefficient.
Use of either infinity or zero as operands may produce an indefinite result. An exponent of octal 1777 and a zero coefficient are packed in this case, and an optional exit provided. Note that zero, infinite, and indefinite results are generated or regenerated in floating arithmetic operations only. The branch instructions test for infinite or indefinite quantities.
Thus the special operand forms (in octal) are:
Whenever infinite, indefinite, or zero results are generated in accordance
with the rules given in Table 35 and Appendix C, only the following octal words
can occur as results:
Note that in these cases the 48 least
significant bits of the result are zeros. Indefinite and zero results generated
in accordance with Table 35 and Appendix C are always positive, but the sign of
infinite results is determined by the usual algebraic sign convention. For
example:
There is no special treatment of zero operands in the Floating Add unit. Zero coefficients and the forms 0000X. . . X and 7777X. . . X are not specially detected, and unstandardized zero results can be produced. (See description of 30 instruction, page 337. )
Overflow and Underflow
Exponents lying outside the range
1777_{8} to +1777_{8} cannot be generated during execution of a
floating point arithmetic instruction or during execution of a Normalize
instruction. An attempt to generate an exponent greater than +1777_{8}
yields an infinite result (overflow case). An attempt to generate an exponent
less than 1777_{8} yields a zero result (underflow case). All cases of
overflow and underflow are listed in Table 36.
Converting Integers to Floating Format
Conversion of
integers to floating point format makes use of the Shift Unit and the zero
constant in increment register B0. The B0 quantity provides for generation of
exponent bias in this case. For example, the instructions:
Note 1. Overflow of Upper Sum: Overflow cannot occur unless one operand is infinite. In this case the eresult is as indicated. If a oneplace Right Shift occurs when the larger operand exponent is equal to +1776_{8}, a correct result with exponent +1777_{8} is generated.
Note 2. Underflow of Exponent During Normalization: The final (B_{j}) are the same as if underflow had not occurred. In particular, if the initial coefficient is zero, (B_{j}) are equal to 60_{8}.
Fixed point addition and subtraction of 60bit numbers are handled in the Long Add Unit (6600). Negative numbers are represented in one's complement notation, and overflows are ignored. The sign bit is in the highorder bit position (bit 59) and the binary point is at the right of the loworder bit position (bit 0).
The Increment Units provide an 18bit fixed point add and subtract facility. Negative numbers are represented in one's complement notation and overflows are ignored. The sign bit is in the highorder bit position (bit 17), and the binary point is at the right of the loworder bit position (bit 0). The Increment Units allow program indexing through the full range of Central Memory addresses.
Fixed point integer addition and subtraction are possible in the Floating Add Unit providing the exponents of both operands are zero and no overflow occurs. The unit performs the one's complement addition (or subtraction) in the upper half of a 98bit accumulator. If overflow occurs, the unit shifts the result one place right and adds one to the exponent, thereby producing a floating point quantity. Thus, care must be used in performing fixed point arithmetic in the Floating Add Unit.
Fixed point integer multiplication is handled in the multiply functional units as a subset operation of the unrounded Floating Multiply (40, 42) instructions. The multiply is double precision (96 bits) and allows separate recovery of upper and lower products. The multiply requires thatboth of the integer operands be converted (by program) to floating format to provide biased exponents. This insures that results are not sensed as underflow conditions. The bias is removed when the result is unpacked.
. 


1)  Pack X2 from X2 and BO  Pack X2 
2)  Pack X3 from X3 and BO  Pack X3 
3)  Normalize X3 in X0 and BO  Normalize X3 (divisor) 
4)  Floating quotient of X2 and X0 to X1  Divide 
5)  Unpack X1 to X1 and B7  Unpack quotient 
6)  Shift X1 nominally left B7 places  Shift to integer position 
.  1)  both integer (247 maximum) operands be in floating format 
and  2)  the divisor be shifted 48 places left 
or  3)  the quotient be shifted 48 places right 
or  4)  any combination of n leftshifts of the divisor and 48n right shifts of the quotient be accomplished. 
This section describes the Central Processor instructions. Instruction grouping follows a somewhat pedagogical approach (i.e., simple to complex) and does not necessarily relate instructions to the functional units (6600 system) which execute them. Central Processor instructions as related to functional units are tabulated in Appendix B, Instruction Execution Times.
TABLE 37. CENTRAL PROCESSOR INSTRUCTION DESIGNATORS


 Specifies one of eight 18bit address registers. 
 Specifies one of eight 18bit index registers; BO is fixed and equal to zero. 
 A 6bit instruction code. 
 A 3bit code specifying one of eight designated registers (e.g., Ai). 
 A 3bit code specifying one of eight designated registers (e. g. , B j). 
 A 6bit constant, indicating the number of shifts to be taken. 
 A 3bit code specifying one of eight designated registers (e.g., Bk). 
 An 18bit constant, used as an operand or as a branch destination (address). 
 Specifies one of eight 60bit operand registers. 
12  BXi  Xj+Xk  Logical Sum of Xj and Xk to Xi  (15 bits) 
Octal Code  Mnemonic Code  Address Field  Instruction Name  Instruction Length 
Program Stop and No Operation
00  PS  .  Program Stop  (30 Bits) 
46  NO  .  No operation (Pass)  (15 Bits) 
Increment
50  SAi  Aj + K  Set Ai to Aj + K  (30 Bits) 
51  SAi  Bj + K  Set Ai to Bj + K  (30 Bits) 
52  SAi  X j + K  Set Ai to X j + K  (30 Bits) 
53  SAi  Xj + Bk  Set Ai to Xj + Bk  (15 Bits) 
54  SAi  Aj + Bk  Set Ai to Aj + Bk  (15 Bits) 
55  SAi  Aj  Bk  Set Ai to Aj  Bk  (15 Bits) 
56  SAi  Bj + Bk  Set Ai to Bj + Bk  (15 Bits) 
57  SAi  Bj  Bk  Set Ai to Bj  Bk  (15 Bits) 
These instructions perform one's complement addition and subtraction of 18bit operands and store an 18 bit result in address register i. Overflow, in itself, is ignored, but an address range fault may result from overflow in this set of instructions.
Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60bit word. Note that an immediate memory reference is performed to the address specified by the final content of address registers A1  A7. The operand read from memory address specified by Al  A5 is sent to the corresponding operand register X1  X5. When A6 or A7 is referenced, the operand from the corresponding X6 or X7 operand register is stored at the address specified by A6 or A7.
NOTE
If, in this category of instructions, the result placed in address register Ai is an address out of range, the following occurs: (Note that this action is independent of an Exit selection on Address Out of Range.) If i = 15: Operand register Xi is loaded with the contents of absolute address zero and the contents of memory location (Ai) are unchanged. If i = 6 or 7: Operand register Xi retains its original contents and the contents of memory location (Ai) are unchanged.
EXAMPLE: Initial Quantities: 50 SAi Aj + K i = 4 K = 234567_{8} SA4 A6 + K j = 6 A4 = 321110_{8} SA4 = 432100_{8} + 234567_{8} A6 = 432100_{8} SA4 = 666667_{8} X4 = 00.....00_{8} Storage location 666667 = 7. . . 75342104600_{8} Final Quantities: A4 = 666667_{8} A6 = 432100_{8} X4 = 7. .. 75342104600_{8}
60  SBi  Aj + K  Set Bi to Aj + K  (30 Bits) 
61  SBi  Bj + K  Set Bi to Bj + K  (30 Bits) 
62  SBi  Xj + K  Set Bi to Xj + K  (30 Bits) 
63  SBi  Xj + Bk  Set Bi to X j + Bk  (15 Bits) 
64  SBi  Aj + Bk  Set Bi to Aj + Bk  (15 Bits) 
65  SBi  Aj  Bk  Set Bi to Aj  Bk  (15 Bits) 
66  SBi  Bj + Bk  Set Bi to Bj + Bk  (15 Bits) 
67  SBi  Bj  Bk  Set Bi to Bj  Bk  (15 Bits) 
Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60bit word.
70  Six  Aj + K  Set Xi to Aj + K  (30 Bits) 
71  SXi  Bj + K  Set Xi to Bj + K  (30 Bits) 
72  SXi  Xj + K  Set Xi to Xj + K  (30 Bits) 
73  SXi  Xj + Bk  Set Xi to Xj + Bk  (15 Bits) 
74  SXi  Aj + Bk  Set Xi to Aj + Bk  (15 Bits) 
75  SXi  Aj  Bk  Set Xi to Aj  Bk  (15 Bits) 
76  SXi  Bj + Bk  Set Xi to Bj + Bk  (15 Bits) 
77  SXi  Bj  Bk  Set Xi to Bj  Bk  (15 Bits) 
These instructions perform one's complement addition and subtraction of 18bit operands and store an 18bit result into the lower 18 bits of operand register Xi. The sign of the result is extended to the upper 42 bits of operand register Xi. An overflow condition is ignored.
Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60bit word. EXAMPLE:
Initial Quantities: 73 SXi Xj + Bk i = 2 X2 = 0. . . 0745321402_{8} SX2 X3 + B1 j = 3, K = 1 X3 = 0_ . . 0652224310_{8} SX2 = 0. . . 0652224310_{8} + 511245_{8} B1= 511245_{8} SX2 = 7. . . 7777735555_{8} Final Quantities: X2 = 7...7777735555_{8} X3 = 0...0652224310_{8} B1 = 511245_{8}
Fixed Point Arithmetic
36  IXi  Xj +Xk  Integer sum of Xj and Xk to Xi  (15 Bits) 
37  IXi  Xi  Xk  Integer difference of Xj and Xk to Xi  (15 Bits) 
47  CXi  Xk  Count the number of "1's" in Xk to Xi  (15 Bits) 