CONTROL DATA
6400/6500/6600 COMPUTER SYSTEMS Reference Manual

INDEX TO CENTRAL PROCESSOR INSTRUCTIONS

NUMERICAL

*Jump to K + Bi and Jump to K if Bi---tests made in Increment unit.
**Jump to K if Xj---tests made in Long Add unit.
Rev. A

ALPHABETICAL

*Jump to K + Bi and Jump to K if Bi---tests made in Increment unit.
**Jump to K if Xj---tests made in Long Add unit.
Rev. A

CONTENTS

2. Central Memory

3. Central Processor

4. Peripheral and Control Processors

5. System Interrupt

6. Manual Control

FIGURES

TABLES

A CONTROL DATA 6000 SERIES COMPUTER SYSTEM

Display console (foreground) - includes a keyboard for manual input and operator control and two 10-inch display tubes for display of problem status and operator directives.

Mainframe (center) - contains 10 Peripheral and Control Processors, Central Processor, Central Memory, some 1/O synchronizers. The main frame in this photo is that of the 6600 Computer System; the mainframesfor the 6400 and 6500 systems differ in physical appearance, depending on options included in the systems.

CONTROL DATA 607 Magnetic Tape Transport (left front) - 1 / 2-inch magnetic tape units for supplementary storage; binary or BCD data handled at 200, 556, or 800 bpi.

CONTROL DATA 626 Magnetic Tape Transport (left rear) - 1-inch magnetic tape units for supplementary storage; binary data handled at 800 bpi.

CONTROL DATA 405 Card Reader (right front) - reads binary or BCD cards at 1200 card per minute rate.

Disk file (right rear) - supplementary mass storage device; holds 500 million bits of information.

1. SYSTEM DESCRIPTION

INTRODUCTION

The CONTROL DATA* 6400, 6500, and 6600 Computer Systems are three large-scale, solid-state, general-purpose digital computing systems. The advanced design techniques incorporated in these systems provide for extremely fast solutions to data processing, scientific, and control center problems, as well as multiprocessing, time-sharing, and management information applications.

Each of the computing systems has at least eleven independent computers (Figure 1-1). Ten of these, constructed with the peripheral and operating system in mind, are Peripheral and Control Processors. Each of these ten has separate memory and can execute programs independently of each other or the Central Processor.

Figure 1-1. CONTROL DATA 6400/6500/6600 Computer Systems

The eleventh computer, the Central Processor, is a very high speed arithmetic device. The common element of the Peripheral and Control Processors and the Central Processor is a large Central Memory.

In solving a problem, one or more Peripheral and Control Processors are used for high speed information transfer in and out of the system and to provide operator control. A number of problems may operate concurrently by time-sharing the Central Processor. (To facilitate this, the Central Processor may operate in Central Memory only within address bounds prescribed by a Peripheral and Control Processor.) Further concurrency is obtained within the Central Processor by parallel action of various functional segments. Similarly, Central Memory is organized in 32 logically independent banks of 4096 words (60-bit). Several banks may be in operation simultaneously, thereby minimizing execution time. The multiple operating modes of all segments of the computer, in combination with high-speed transistor circuits, produce a very high over-all computing speed.

Figure 1-2.Concurrent Operations in the 6400/6500/6600

The Peripheral and Control Processor input/output facility provides a flexible arrangement for very high speed communication with a variety of I/O devices. Some of the I/O devices available with the 6400, 6500, and 6600 systems are listed below. (Refer to the 6000 Series Peripheral Reference Manual for additional external equipment information. )

• Console Display: a cathode ray tube console with manual keyboard. This program-controlled unit displays problem status on two cathode ray tubes and handles operator directives from an alphanumeric keyboard similar to a standard typewriter keyboard.
• Disk Systems: mass storage disk files providing nominal storage of 500 million bits or 1. 3 billion bits.
• Magnetic Tape Transports: 1-inch magnetic tape units which handle binary data recording at 800 bits per inch on tapes up to 2400 feet long.
• Satellite Coupler: a systems expansion device which permits direct connection between any two 6400 or 6600 systems via two standard 12-bit bidirectional data channels.
• Data Channel Converter: a device which permits 6400, 6500, and 6600 systems to use CONTROL DATA 3000 Series peripheral equipment. Examples of available 3000 Series peripheral equipment are card equip- ment (readers /punches), magnetic tape equipment, and line printers.

SYSTEMS CHARACTERISTICS SUMMARY

System Characteristics

• Large-scale, general-purpose computer system
• 11 independent computers; 12 in the Dual Processor 6500 system
  • 1 Central Processor (60-bit); 2 Central Processors in the 6500 system
  • 10 Peripheral and Control Processors (12-bit)
  Central Memory (60-bit)
  Display console and keyboard
• System communicates with a variety of external equipment
  • Disk files
  • Magnetic tapes
  • Card equipment
  • Printers
• Central Memory common to the system computers
• Maximum Central Memory storage capability 131, 072 words (60-bit)

Major Cycle = 1000 ns (nanoseconds)

Minor Cycle = 100 ns

Memory organized in 32 banks of 4096 words

Multiphase

• Central Processor instructions

Arithmetic, logical, indexing, branch

• Peripheral and Control Processor instructions Add/Subtract, logical, input/output, access to Central Processor and Central Memory
• Each Peripheral and Control Processor has 12-bit 4096-word memory
• Solid-state system

Transistor logic

Central Processor Characteristics

• 10 arithmetic and logical units

  Add	Shift
  Multiply	Branch
  Multiply	Boolean
  Divide	Increment
  Long add	Increment

• 24 operating registers for functional units

8 operand (60-bit)

8 address (18-bit)

8 increment (18-bit)

• 8 transistor registers (60-bit) hold 32 instructions (15-bit) or 16 instructions (30-bit) or a combination of the two for servicing functional units.

6400 and 6500

• Unified arithmetic section, operating in sequential manner (one per processor in 6500)
• 24 operating registers (one set per processor in 6500)

8 operand (60-bit)

8 address (18-bit)

8 increment (18-bit)

• Instruction Buffer register (60-bit)

Common Central Processor Characteristics

• Floating point arithmetic

Single and double precision

Optional rounding and normalizing

• Format

Integer coefficient - 48 bits

Biased exponent - 11 bits (210)

Coefficient sign - 1 bit

• Fixed point arithmetic (subset of floating point arithmetic)

Full 60-bit add/subtract

• Controlled and started by Peripheral and Control Processors
• Addresses in Central Memory relative

Peripheral and Control Processor Characteristics

• 10 identical processors (characteristics as listed are per processor except as noted)
• 4096-word magnetic core memory (12-bit)
• Random access, coincident - current

Major Cycle = 1000 ns

Minor Cycle = 100 ns

• 12 input/output channels

All channels common to all processors

Maximum transfer rate per channel - one word/major cycle

All 12 channels may be active simultaneously

All channels 12-bit bi-directional

• Real-time clock (period = 4096 major cycles)
• Instructions

Add/Subtract

Logical

Branch

Input / Output

Central Processor access

Central Memory access

• Average instruction execution time = two major cycles
• Indirect addressing
• Indexed addressing

Central Memory Characteristics

• 131, 072 words (maximum size)
• 60-bit words
• Memory organized in 32 logically independent banks of 4096 words with corresponding multiphasing of banks; (32 banks is maximum memory size)
  
  Figure 1-3. Block Diagram of 6600 System

• Random access, coincident-current, magnetic core
• One major cycle for read-write
• Maximum memory reference rate to all banks - one address/minor cycle
• Maximum rate of data flow to/from memory - one word/minor cycle

Display Console Characteristics

• Two display tubes
• Modes

character

dot

• Character size

Large - 16 characters/line

Medium - 32 characters/line

Small - 64 characters /line

• Characters

26 alphabetic

10 numeric

11 special

Figure 1-4.Block Diagram of 6400 and 6500 Systems

SYSTEMS OPTIONS

The foregoing summary of characteristics assumed a 6400, 6500, or 6600 system with 10 Peripheral and Control Processors, a Central Processor (except for the 6500 system with its two identical Central Processors), and Central Memory with 131, 072 words (60-bit) of magnetic core storage.

Options listed below are available within each system unless otherwise noted.

• Central Memory with 131, 072 words (60-bit) of magnetic core storage.
• Central Memory with 65, 536 words (60-bit) of magnetic core storage. (This is the minimum Central Memory size available for the 6500 Computer System. )
• Central Memory with 32, 768 words (60-bit) of magnetic core storage.
• Extended Core Storage (Refer to ECS Reference Manual) available in the following sizes:

125,952 words (60-bit)

251,904 words (60-bit)

503,808 words (60-bit)

1,007,616 words (60-bit)

2,015,232 words (60-bit)

• Extended Core Storage Controller: couples up to 2, 015, 232 words of Extended Core Storage from one to four 6400, 6500, or 6600 central computers) or Augmented I/O Buffer and Control unit(s) in any combination.
• Augmented I/O Buffer and Control: includes 16, 384 words (60-bit) of magnetic core storage and 10 Peripheral and Control Processors with storage.
• Central Processor Monitor Facility (Central and Monitor Exchange Jump instructions):Refer to the publications for Standard Options 10103 and 10104.

2. CENTRAL MEMORY

ORGANIZATION

Central Memory is organized into 32K, 65K, or 131K words (60-bit) in 8, 16, or 32 banks of 4096 words each. The banks are logically independent, and consecutive addresses go to different banks. Banks may be phased into operation at minor cycle intervals, resulting in very high Central Memory operating speed. The Central Memory address and data control mechanisms permit a word to move to or from Central Memory every minor cycle.

ADDRESS FORMAT

The location of each word in Central Memory is identified by an assigned number (address), which consists of 18 bits. Address formats are shown below for 8-bank(32K), 16-bank (65K), and 32-bank (131K) systems. Within the address format, the bank portion specifies one of 8, 16, or 32 banks; the 12-bit address defines one of 4096 separate locations within the specified bank. Addresses written or compiled in the conventional manner reference consecutive banks and hence make most efficient use of the bank phasing feature.

CENTRAL MEMORY ACCESS

References to Central Memory from all areas of the system (Central Processor and Peripheral and Control Processors) go to a common address clearing house called a stunt box and are sent from there to all banks in Central Memory. The stunt box accepts addresses from the various sources under a priority system and at a maximum rate of one address every minor cycle. *Minor cycle=100 ns

An address is sent to all banks, and the correct bank, if free, accepts the address and indicates this to the stunt box. The associated data word is then sent to or stored from a central data distributor. The bank ignores the address if it is busy processing a previous address. The stunt box issues addresses at a maximum rate of one every minor cycle.

The stunt box saves, in a hopper mechanism, each address that it sends to Central Memory and then reissues it (and again saves it) under priority control in the event it is not accepted because of bank conflict. The address issue-save process repeats until the address is accepted, at which time the address is dropped from the hopper and the read or store data word is distributed. A fixed time lapse from addressissue to the memory-accept synchronizes the action taken.

The hopper (i. e., a previously unaccepted address) has highest priority in issuing addresses to Central Memory. The Central Processor and Peripheral and Control Processors (all 10 share a common path to the stunt box) follow in that order.

A data distributor which is common to all processors handles all data words to and from Central Memory (the Peripheral and Control Processors share one read path and one write path to the distributor). A series of buffer registers in the distributor provides temporary storage for words to be written into storage when the addresses are not immediately accepted because of bank conflict.

Each group of four banks communicates with the distributor on separate 60-bit read and write paths, but only one word moves on the data paths at one time. However, words can move at minor cycle intervals between the distributor and Central Memory or distributor and address-sender.

Data words and addresses are correlated by control information (tags) entered in the stunt box with the address. The tags define the address sender, origin/ destination of data, and whether the address is a Read, Write, or Exchange Jump address.

MEMORY PROTECTION

All Central Processor references to Central Memory for new instructions, or to read and store data, are made relative to the Reference Address. The Reference Address defines the lower limit of a Central Memory program. Changes to the Reference Address permit easy relocation of programs in Central Memory.

During an Exchange Jump, an 18-bit Reference Address and an 18-bit Field Length (parts of the Exchange Jump package) are loaded into their respective registers to define the Central Memory limits of the program initiated by the Exchange Jump.

The relationship between absolute memory address, relative memory address, Reference Address (RA), and Field Length (FL) is indicated in Figure 2-1.

Figure 2-1. Memory Map

The following relationships must be true if the program is to operate within its bounds:

RA <= (RA + P) < (RA + FL) (Absolute Memory Addresses), or

0 <= P < FL (Relative Memory Addresses)

NOTE

1. FL is the number of 60-bit words comprising the program, not an address.
2. To avoid possible "artificial" range faults, instructions should not be stored near the upper limit address of the Field Length. For example, using absolute address [(RA + FL) - 1] for an instruction produces a range fault when the (look-ahead) Read Next Instruction occurs to (RA + FL). Data should always be stored in addresses near or approaching absolute location (RA + FL), rather than instructions.

An optional exit condition (EM in the Exchange Jump package) allows the Central Processor to stop on a memory reference outside the limits expressed above.

3. CENTRAL PROCESSOR

ORGANIZATION

The Central Processor is an extremely high-speed arithmetic processor which communicates only with Central Memory. It consists (functionally) of an arithmetic unit and a control unit. The arithmetic unit contains all logic necessary to execute the arithmetic, manipulative and logical operations. The control unit directs the arithmetic operations and provides the interface between the arithmetic unit and Central Memory. It also performs instruction fetching, address preparation, memory protection, and data fetching and storing.

The Central Processor is isolated from the Peripheral and Control Processors and is thus free to carry on high-speed computation unencumbered by input/output requirements.

The organization of the Central Processor in the 6400 system differs from the 6600 Central Processor in two important respects. The 6500 system has two Central Processors; each similar to the 6400 Central Processor. Central Processor differences are tabulated in Table 3-1.

TABLE 3-1. CENTRAL PROCESSOR. DIFFERENCES

The following discussion details the operation of the Central Processor in the 6600 system. With the exception of differences noted in the above table (and the inherent effects on Central Processor operation), the 6400 system Central Processor operation is identical, Each of the two 6500 Central Processors operates identically with the 6400 Central Processor.

Programs for the Central Processor are held in Central Memory. A program is begun by an Exchange Jump instruction from a Peripheral and Control Processor. This instruction also specifies a segment of Central Memory for the central program, specifies the mode of exit (normal or error) of the program, and sets initial quantities in the X, B, and A registers.

High speed in the Central Processor depends first on minimizing memory references. Twenty-four registers are provided to lower the Central Memory requirements for arithmetic operands and results. These 24 are divided into:

• 8 address registers of 18 bits in length
• 8 increment registers of 18 bits in length
• 8 operand registers of 60 bits in length

Eight 60-bit registers are provided to hold instructions (6600), thereby limiting the number of memory reads for repetitive instructions, especially in inner loops. Multiple banks of Central Memory are also provided to minimize memory reference time. References to different banks of memory may be handled without wait.

Speed of operation in a conventional computer is also limited by the serial manner in which instructions are executed; instructions are executed sequentially in time with little or no concurrency.

In the 6600 Computer System, this delay is minimized by providing 10 arithmetic (functional) units and a reservation control. Unrelated instructions are executed simultaneously, provided no conflicts exist in the arithmetic units.

The 6400 or 6500, with its unified arithmetic section, executes instructions serially, with little concurrency.

Programs are written for the Central Processor in a conventional manner, specifying a sequence of arithmetic and control operations to be executed. Each instruction in a program is brought up in its turn from one of the instruction registers. These registers are filled from Central Memory in a manner sufficient to keep a reasonable flow of instructions available. A branch to another area of the program voids the old instructions in the registers and brings in new instructions. When a new instruction is brought up, a test is made on it to determine which of the 10 arithmetic units is needed, if it is busy, and if reservation conflict is possible. If the unit is free and no conflict is present, the entire instruction is given to the specified arithmetic unit for further action. Another instruction may then be brought up for issuance.

The original sequence of the program is established at the time each instruction is issued. Only those operations which depend on previous steps prevent the issuing of instructions, and then only if the steps are incomplete. The reservation control keeps a running account of the address, increment, and operand registers and of the arithmetic units in order to preserve the original sequence.

On occasion, a program may use an Increment Store instruction to modify the contents of a memory location holding a subsequent instruction. In the 6600, this modification must occur before the instruction is read from Central Memory into the stack, for once in the stack the instruction can not be so modified. To avoid this potential problem, modification of any subsequent instruction words should be restricted to relative locations >_ (P) + 8. This rule applies equally to both "in-stack" loops and to other programs where, under certain conflict conditions, the Central Processor of the 6600 may continue reading instruction words from Central Memory while delaying execution of a previously issued Increment Store instruction.

Nearly all Central Memory references for information or instructions are made on an implicit or secondary basis. Instructions are fetched from memory only if the instruction registers are nearly empty (or when ordered by a branch). Information is brought to or from the operand registers only when appropriate address registers are referenced during the course of a program. Such references are also accounted for in the reservation control.

All Central Processor references to Central Memory are made relative to the lower boundary address assignedby a Peripheral and Control Processor. A Central Processor program may therefore be relocated in Central Memory by modifying the boundaries only. Any attempt by the Central Processor to reference memory outside of its boundaries causes an immediate exit which can be readily examined by a Peripheral and Control Processor and displayed for the operator.

The Exchange Jump instruction described on page 3-9 starts a central program. This instruction starts a sequence of Central Memory references which exchanges 16 words in memory with the contents of the address, increment, and operand registers of the Central Processor. Also exchanged are the program address, the Central Memory and Extended Core Storage boundaries, and choice of program exit. This instruction may be executed by any Peripheral and Control Processor and acts as an interrupt to an active central program as well as a start from an inactive state. The Exchange Jump is used by the operating system to switch between two central programs, leaving the first program in a usable state for later re-entry.

CENTRAL PROCESSOR PROGRAMMING

Central Processor program instructions are stored in Central Memory. A 60-bit memory location may hold 60 data bits, four 15-bit instructions, two 30-bit instructions or a combination of 15 or 30-bit instructions. Figure 3-1 shows all instruction combinations in a 60-bit word and the two instruction word formats.

The Central Processor reads 60-bit words from Central Memory and stores them in an instruction stack which is capable of holding up to eight 60-bit words.

Each instruction in turn is sent to a series of instruction registers for interpretation and testing and is then issued to one of 10 functional units for execution. The functional units obtain the instruction operands from and store results in the 24 operating registers. The reservation control records active operating registers and functional units to avoid conflicts and insure that the original instructions do not get out of order.

Functional Units

The 10 functional units in the 6600 system handles the requirements of the various instructions. The Multiply and Increment units are duplexed, and an instruction is sent to the second unit if the first is busy. The general function of each unit is listed in Table 3-2. TABLE 3-2. FUNCTIONAL UNITS

Instruction Formats

Groups of bits in an instruction are identified by the letters f, m, i, j, k, and K (Figure 3-1). All letters represent octal digits except K,which is an 18-bit constant. The f and m digits are the operation code and identify the type of instruction. In a few instructions the i designator becomes a part of the operation code.

In most 15-bit instructions the i, j, and k digits each specify one of eight operating registers where operands are found and where the result of the operation is to be stored. In other 15-bit instructions, the j and k digits provide a 6-bit shift count.

In 30-bit instructions the i and j digits each specify one of eight operating registers where one operand is found and where the result is to be stored, and K is taken directly as an 18-bit second operand.

NOTE

In the 6600, it is permissible to pack the upper-order 15 bits (fmij portion) of a 30-bit instruction in the lowerorder 15-bit portion of an instruction word. When this 30- bit instruction is executed, the lower-order 15-bits of K are taken from the upper-order 15 bits of the instruction word. In the 6400 and 6500, any 30-bit instruction with its fmij portion packed in the lower-order 15 bits of an instruction word will be executed as a STOP instruction.

Operating Registers In order to provide a compact symbolic language, the 24 operating registers are identified by letters and numbers:

A = address register (A0, Al . . . A7)

B =increment register (B0, 131 . . . B7)

X =operand register (X0, X1 . . . X7)

The operand registers hold operands and results for servicing the functional units. Five registers (X1 - X5) hold read operands from Central Memory, and two registers (X6 - X7) hold results to be sent to Central Memory (Figure 3-2). Operands and results transfer between memory and these registers as a result of placing a quantity into a corresponding address register (Al - A7).

Placing a quantity into an address register A1 - A5 produces an immediate memory reference to that address and reads the operand into the corresponding operand register X1 - X5. Similarly, placing a quantity into address register A6 or A7 stores the word in the corresponding X6 or X7 operand register in the new address.

Figure 3-2. Central Processor Operating Registers

The increment instructions place a result in address register Ai (where "i" = 0 to 7) in three ways:

• By adding an 18-bit signed constant K to the contents of any A, B, or X register.
• By adding the content of any B register to any A, B, or X register.
• By subtracting the content of any B register from any A register or any other B register.

The A0 and X0 registers are independent and have no connection with Central Memory. They may be used for scratch pad or intermediate results. Note the special use of A0 and X0 when executing Extended Core Storage communication instructions.

The B registers have no connection with Central Memory. The BO register is fixed to provide a constant zero (18-bit) which is useful for various tests against zero, providing an unconditional jump modifier, etc. In general, the n registers provide means for program indexing. For example, B4 may store the number of times a program loop has been traversed, thereby providing a terminal condition for a program exit.

An Exchange Jump instruction from a Peripheral and Control Processor enters initial values in the operating registers to start Central Processor operation. Subsequent address modification instructions executed in the increment functional units provide the addresses required to fetch and store data.

Program Address
An 18-bit P register serves as a program address counter and holds the address for each program step. P is advanced to the next program step in the following ways:

1. P is advanced by one when all instructions in a 60-bit word have been extracted and sent to the instruction registers.
2. P is set to the address specified by a Go To . . . (branch) instruction. If the instruction is a Return Jump, (P) + 1 is stored before the branch to allow a return to the sequence after the branch.
3. P is set to the address specified in the Exchange Jump package.

All branch instructions to a new program start the program with the instruction located in the highest order position of the 60-bit word.

Exchange Jump A Peripheral and Control Processor Exchange Jump instruction starts or interrupts the Central Processor and provides Central Memory with the first address (which is the address in the Peripheral and Control Processor A register) of a 16-word package in Central Memory. The Exchange Jump package (Figure 3-3) provides the following information on a program to be executed:

1. Program address (P)
2. Reference Address for Central Memory (RA _CM )
3. Field length of program for Central Memory (FLCM)
4. Reference Address for Extended Core Storage (RA_ECS
5. Field length of program for Extended Core Storage (FL_ECS)*
6. Program exit mode (EM)
7. Initial contents of the eight A registers
8. Initial contents of the eight X registers
9. Initial contents of B registers B1 - B7 (BO is fixed at 0)

The Central Processor enters the information about a new program into the appropriate registers and stores the corresponding and current information from the interrupted program at the same 16 locations in Central Memory. Hence, the controlling information for two programs is exchanged. A later Exchange Jump may return an interrupted program to the Central Processor for completion. The normal relation of the A and X registers (described earlier) is not active during the Exchange Jump so that the new entries in A are not reflected into changes in X.

PROGRAMMING NOTE

When an Exchange Jump interrupts the Central Processor, several steps occur to insure leaving the interrupted program in a usable state for re-entry:

1. Issue of instructions halts after issuing all instructions from the current instruction word in the instruction stack.
2. The Program Address register, P, is set to the address of the next instruction word to be executed.
3. The issued instructions are executed, and then
4. The parameters for the two programs are exchanged.

A subsequent Exchange Jump can then re-enter the interrupted program at the point it was interrupted, with no loss of program continuity.

To preserve the integrity of an "in-stack" loop (in the event of an Exchange Jump), it is illegal to modify the contents of any memory address which holds an executable instruction (or instruction word) contained within the loop.

All Central Processor references to Central Memory for new instructions, or to fetch and store data, are made relative to the Reference Address. This allows easy relocation of a program in Central Memory. The Reference Address or beginning address and the Field Length define the Central Memory limits of the program. An Exit Selection allows the Central Processor to stop on a memory reference outside these limits.

The Program Address register P defines the location of a program step within the limits prescribed. Each reference to memory to fetch instructions is made to the address specified by P + RA. Hence program relocation is conveniently handled through a single change to RA.

A P = 0 condition specifies address zero and hence RA. This address is reserved for recording program exit (error) conditions and should not, therefore, be used to store data or instructions of a program.

Exit Mode

Typically, the Reference Address (RA) for any program is left cleared to all zeros. When an error exit is taken, the Central Processor records at RA the exit condition (upper 2 octal digits only) and the Program Address at exit time (refer to the format below).

NOTE
The Exit condition(s) recorded at RA comprises all the Exit conditions detected since the last Exchange Jump, regardless of whether they were selected. Thus, com- binations of error Exit conditions (03, 05, 06 or 07) can appear at RA:

1. When at least one Exit condition was selected and the selected condition plus another condition occur- red since the last Exchange Jump, or
2. When more than one Exit condition was selected and each occurred in the same minor cycle.

On an Address Out of Range, hardware action differs from that outlined above. In some cases, a stop occurs when an address is out of bounds even though an Exit mode stop is not selected for this condition. Table 3-3 summarizes hardware action for operations which may reference addresses that are out of bounds.

TABLE 3-3. EXIT MODE: ADDRESS OUT OF BOUNDS

Action After Exit Mode or Normal Stop
Typically, a Peripheral and Control Processor periodically searches for an unchanging Central Processor Program Address register (any value) to determine if the Central Processor has stopped. Once it has been determined that the Central Processor has stopped, the examining Peripheral and Control Processor can transfer control to an error routine to determine the nature of the condition causing the Stop. Figure 3-4 illustrates sample steps for processing Central Processor stops (either Exit mode or normal).

Figure 3-4. Detecting and Handling Central Processor Stops

Floating Point Arithmetic

Format
Floating point arithmetic takes advantage of the ability to express a number with the general expression kBⁿ where:

k = coefficient

B = base number

n = exponent, or power to which the base number is raised

The base number is constant (2) for binary-coded quantities and is not included in the general format. The 60-bit floating-point format is shown below. The binary point is considered to be to the right of the coefficient, thereby providing a 48-bit integer coefficient, the equivalent of about 14 decimal digits. The sign of the coefficient is carried in the highest order bit of the packed word. Negative numbers are represented in one's complement notation.

The 11-bit exponent carries a bias of 2¹⁰ (2000₈) when packed in the floating point word (biased exponent sometimes referred to as characteristic). The bias is removed when the word is unpacked for computation and restored when a word is packed into floating format. Table 3-4 lists (in decimal and octal notation) the complete range of permissible exponents and the octal form of the corresponding positive and negative floating point words.

Thus, a number with a true exponent of 342 would appear as 2342; a number with a true exponent of -160 would appear as 1617. Exponent arithmetic is done in one's complement notation. Floating point numbers can be compared for equality and threshold.

TABLE 3-4. RANGE OF PERMISSIBLE EXPONENTS

Normalizing and Rounding
Normalizing a floating point quantity shifts the coefficient left until the most significant bit is in bit 47. Sign bits are entered in the low-order bits of the coefficient as it is normalized. Each shift decreases the exponent by one.

A round bit is added (optionally) to the coefficient during an arithmetic process and has the effect of increasing the absolute value of the operand or result by one-half the value of the least significant bit. Normalizing and rounding are not automatic during pack or unpack operations so that operands and results may not be normalized.

Single and Double Precision
The floating point arithmetic instructions generate double-precision results. Use of unrounded operations allows separate recovery of upper and lower half results with proper exponents; only upper half results can be obtained with rounded operations.

Double length registers appear as follows:

Range Definitions
A result with an exponent so large that it exceeds the upper limit of octal 3777 (overflow case) is treated as an infinite quantity. A coefficient of allzeros and an exponent of octal 3777 or 4000 is packed for this case. An optional exit is provided when an attempt is made to use an infinite operand in the floating arithmetic units since its use may propagate an indefinite result as shown in Table 3-5. No error exit occurs when an infinite or indefinite result is generated in a functional unit.

TABLE 3-5. INDEFINITE FORMS

A result the exponent of which is less than the lower limit of octal 0000 (underflow case) is treated as a zero quantity. This quantity is packed with a zero exponent and zero coefficient. No exit is provided for underflow. A result with an exponent of octal 0000 and a coefficient which is not zero is a non-zero quantity and is packed with a zero exponent and the non-zero coefficient.

Use of either infinity or zero as operands may produce an indefinite result. An exponent of octal 1777 and a zero coefficient are packed in this case, and an optional exit provided. Note that zero, infinite, and indefinite results are generated or regenerated in floating arithmetic operations only. The branch instructions test for infinite or indefinite quantities.

In all floating arithmetic operations, an attempt to normalize an indefinite quantity returns the original quantity, e. g., if the number 17770237. . . were to be normalized, the result would be the same as the original number. Note that Exit mode does not occur on detecting an indefinite quantity in the Shift Unit.

Exit mode tests for infinite and indefinite operands are made only in the Floating Add, Multiply, and Divide Units. The 12 most significant bits of each operand are tested for these special forms.

In the Multiply and Divide Units (but not in the Floating Add Unit) there is a special test for zero operands as determined by the 12 most significant bits.

Thus the special operand forms (in octal) are:

Whenever infinite, indefinite, or zero results are generated in accordance with the rules given in Table 3-5 and Appendix C, only the following octal words can occur as results:

Note that in these cases the 48 least significant bits of the result are zeros. Indefinite and zero results generated in accordance with Table 3-5 and Appendix C are always positive, but the sign of infinite results is determined by the usual algebraic sign convention. For example:

There is no special treatment of zero operands in the Floating Add unit. Zero coefficients and the forms 0000X. . . X and 7777X. . . X are not specially detected, and unstandardized zero results can be produced. (See description of 30 instruction, page 3-37. )

Overflow and Underflow
Exponents lying outside the range -1777₈ to +1777₈ cannot be generated during execution of a floating point arithmetic instruction or during execution of a Normalize instruction. An attempt to generate an exponent greater than +1777₈ yields an infinite result (overflow case). An attempt to generate an exponent less than -1777₈ yields a zero result (underflow case). All cases of overflow and underflow are listed in Table 3-6.

Converting Integers to Floating Format
Conversion of integers to floating point format makes use of the Shift Unit and the zero constant in increment register B0. The B0 quantity provides for generation of exponent bias in this case. For example, the instructions:

• Sum of Bj and Bk to Xi (where i = 2, j = 3, k = 4)
• Pack Xi from Xk and Bj (where i = 2, j = 0, k = 2)

Note 1. Overflow of Upper Sum: Overflow cannot occur unless one operand is infinite. In this case the eresult is as indicated. If a one-place Right Shift occurs when the larger operand exponent is equal to +1776₈, a correct result with exponent +1777₈ is generated.

Note 2. Underflow of Exponent During Normalization: The final (B_j) are the same as if underflow had not occurred. In particular, if the initial coefficient is zero, (B_j) are equal to 60₈.

Fixed Point Arithmetic

Fixed point addition and subtraction of 60-bit numbers are handled in the Long Add Unit (6600). Negative numbers are represented in one's complement notation, and overflows are ignored. The sign bit is in the high-order bit position (bit 59) and the binary point is at the right of the low-order bit position (bit 0).

The Increment Units provide an 18-bit fixed point add and subtract facility. Negative numbers are represented in one's complement notation and overflows are ignored. The sign bit is in the high-order bit position (bit 17), and the binary point is at the right of the low-order bit position (bit 0). The Increment Units allow program indexing through the full range of Central Memory addresses.

Fixed point integer addition and subtraction are possible in the Floating Add Unit providing the exponents of both operands are zero and no overflow occurs. The unit performs the one's complement addition (or subtraction) in the upper half of a 98-bit accumulator. If overflow occurs, the unit shifts the result one place right and adds one to the exponent, thereby producing a floating point quantity. Thus, care must be used in performing fixed point arithmetic in the Floating Add Unit.

Fixed point integer multiplication is handled in the multiply functional units as a subset operation of the unrounded Floating Multiply (40, 42) instructions. The multiply is double precision (96 bits) and allows separate recovery of upper and lower products. The multiply requires thatboth of the integer operands be converted (by program) to floating format to provide biased exponents. This insures that results are not sensed as underflow conditions. The bias is removed when the result is unpacked.

An integer divide takes several steps and makes use of the Divide and Shift Units. For example, an integer quotient X1 = X2/X3 is produced by the following steps:

Description of Central Processor Instructions

This section describes the Central Processor instructions. Instruction grouping follows a somewhat pedagogical approach (i.e., simple to complex) and does not necessarily relate instructions to the functional units (6600 system) which execute them. Central Processor instructions as related to functional units are tabulated in Appendix B, Instruction Execution Times.

TABLE 3-7. CENTRAL PROCESSOR INSTRUCTION DESIGNATORS

Preceding the description of each instruction is the octal code, mnemonic code and address field, the instruction name and length. Mnemonic codes and address field mnemonics are from ASCENT, a Central Processor Assembly language. The equivalent COMPASS mnemonics are given in Appendix D.

EXAMPLE:

Instruction formats are also given; parallel lines within a format indicate these bits are not used in the operation.

Program Stop and No Operation

This instruction stops the Central Processor at the current step in the program. An exchange Jump is necessary to restart the Central Processor.

This instruction is a "do-nothing" instruction that is typically used to pad the program between certain program steps. EXAMPLE:

In this example, a Pass instruction is used to pad the remainder of the word at P. Since the next instruction is 30 bits, it cannot fit in P and must be placed in P + 1.

Increment

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18- bit result in address register i. Overflow, in itself, is ignored, but an address range fault may result from overflow in this set of instructions.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word. Note that an immediate memory reference is performed to the address specified by the final content of address registers A1 - A7. The operand read from memory address specified by Al - A5 is sent to the corresponding operand register X1 - X5. When A6 or A7 is referenced, the operand from the corresponding X6 or X7 operand register is stored at the address specified by A6 or A7.

NOTE
If, in this category of instructions, the result placed in address register Ai is an address out of range, the following occurs: (Note that this action is independent of an Exit selection on Address Out of Range.) If i = 1-5: Operand register Xi is loaded with the contents of absolute address zero and the contents of memory location (Ai) are unchanged. If i = 6 or 7: Operand register Xi retains its original contents and the contents of memory location (Ai) are unchanged.

EXAMPLE:				Initial Quantities:
   50  SAi     Aj + K	i = 4	K = 2345678
       SA4     A6 + K	j = 6	A4 = 3211108
       SA4 = 4321008 +	2345678	A6 = 4321008
       SA4 = 6666678	X4 = 00.....008
                      Storage location 666667 = 7. . . 753421046008
                      Final Quantities:
                      A4 = 6666678
                      A6 = 4321008
                      X4 = 7. .. 753421046008

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18-bit result in increment register Bi. An overflow condition is ignored.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word.

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18-bit result into the lower 18 bits of operand register Xi. The sign of the result is extended to the upper 42 bits of operand register Xi. An overflow condition is ignored.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word. EXAMPLE:

					Initial Quantities:
	73	SXi	Xj + Bk	i = 2	X2 = 0. . . 07453214028
		SX2	X3 + B1	j = 3, K = 1	X3 = 0_ . . 06522243108
		SX2 =	0. . . 06522243108 + 5112458   B1= 5112458
		SX2 =	7. . . 77777355558
					Final Quantities:
                              X2 = 7...77777355558
                              X3 = 0...06522243108
                              B1 =         5112458

Fixed Point Arithmetic

This instruction forms a 60-bit one's complement sum of the quantities from operand registers Xj and Xk and stores the result in operand register Xi. An overflow condition is ignored.

This instruction forms the 60-bit one's complement difference of the quantities from operand registers Xj (minuend) and Xk (subtrahend) and stores the result in operand register Xi. An overflow condition is ignored.

This instruction counts the number of "1 's" in operand register Xk and stores the count in the lower order 6 bits of operand register Xi. Bits 6 through 59 are cleared to zero.

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